I. Field of the Invention
The present invention relates to digital signal processing. More particularly, the present invention relates to a novel and improved method for generating a single bit digital signal from a multibit digital signal.
II. Description of the Related Art
In the design of an electrical circuit, a need often arises to convert a multibit digital signal into a single bit digital signal. A typical circuit for performing such a conversion function is comprised of a counter and a comparator. In this configuration the counter is clocked to produce an N-bit counter output value which is provided to one set of inputs to the comparator. An N-bit input value is provided to the other set of comparator inputs. The comparator compares the binary magnitude of the N-bit input value with the binary magnitude of the continuously counting counter value to generate a single bit periodic digital signal. The duty cycle of this resulting single bit digital signal is proportional to the N-bit input value; hence, the term pulse width modulation (PWM) is used.
In addition to the applications of such a signal within a digital circuit, the single bit digital signal also is commonly used to allow digital circuitry to interface with analog circuitry. In this application the single bit digital signal output from the comparator is low-pass filtered to create an analog signal. The purpose of the low-pass filter is to average the discrete levels of the single bit digital signal to produce a constant analog signal output. The duty cycle of the single bit digital signal determines the value of the resulting analog signal at the output of the filter.
The disadvantage of the PWM signal is that within a single cycle all like bits come consecutively, meaning there is no more than one transition from logic value "1" to logic value "0" and from logic value "0" to logic value "1" per period. The single rising and falling edge results in the limitation of applications of such a signal within a digital circuit.
If the single bit signal is converted to analog, this disadvantage also adversely affects the characteristics of the analog signal created. To keep the analog signal output from increasing during the portion of the PWM period that is logic value "1" and then decreasing during the portion of the PWM period that is logic value "0"the low-pass filter selected must have a low cutoff frequency. However the low cutoff frequency also slows the reaction time of the analog signal output to changes in the value of the input digital signal.
It is therefore the objective of the present invention to provide a novel and improved apparatus and method for converting a multibit digital signal into a single bit digital signal.
It is yet another object of the present invention to provide a circuit and method for converting a multibit digital signal to an analog signal with an improved relationship between the alternating current (AC) component on and response time of the resulting analog signal.